Leakage current is commonly found in memories including, for example, static random access memories (SRAM), register files, etc. Generally, the higher the number of ports (e.g., read and/or write ports) for the memory, the higher the current leaks. Existing approaches have different methods to reduce the leakage current. For example, in some approaches the ground reference level (e.g., voltage VSS) is raised and/or the operational supply voltage (e.g., voltage VDD) is lowered, e.g., by a voltage dropped across a diode at the whole memory array level. In some approaches, when the memory is segmented, the whole segment has its voltage VSS and/or voltage VDD raised and/or lowered. Raising voltage VSS and/or lowering voltage VDD at the segment level or the memory array level affect the whole segment or memory array operation, including the power consumption and/or speed.
In some approaches, the bit line of the read port for the whole column of memory cells is floated during the retention period to reduce the leakage current. In these approaches, the whole accessed column is disabled during the time the bit line is floated, and before accessing the data, raising the bit line back to voltage VDD is required, which impacts the dynamic power because the VDD nodes for the whole segment/array are coupled together and have a large capacitance. As a result, the memory speed is compromised.
In some other approaches, high threshold voltage (HVT) bit cells are used, but the memory access time is then also increased.
Like reference symbols in the various drawings indicate like elements.